1. Field of the Invention
The present invention relates to a memory system which is provided with memory cells packed with high density and capable of non-destructive, dynamic and semi-static readout of memory information.
2. Description of the Prior Art
It is well-known in the art that semiconductor memories are roughly divided into a dynamic memory (d-RAM), a static memory (S-RAM), a read only memory (ROM) and a serial memory. The memory of the present invention is of the dynamic memory type in terms of operation. In the static memory, information of conduction and non-conduction of two flip-flop transistors is represented by digital information "0" and "1" and this information is maintained as long as the power source voltage is applied, and it can be considered that the information can be stored substantially permanently under the condition that the power source voltage is applied.
An existing 4K, 16K or 64K dynamic memory, or a 256K memory recently published in ISSCC (1980) employs a one-transistor one-capacitor type memory cell which comprises one MOSFET and one capacitor.
Generally, in the case where information (the amount of charges) stored in such a capacitor is read out by the conduction and non-conduction of one gate (word line) of the transistor serving as a switch, a voltage variation on a bit line is capacitively divided such that {C.sub.S /(C.sub.S +C.sub.B)}V.sub.S to provide a small signal voltage, where V.sub.S is the voltage stored in the capacitor, C.sub.S is the storage capacitance of the capacitor and C.sub.B is a parasitic capacitance of the bit line. Further, in this type of memory, once the information has been read out, the charges stored in the capacitor flow out therefrom, so that a refresh operation is needed for re-writing. It is necessary to provide a circuit arrangement on the bit line so that the reduced signal voltage by the capacitive division may be amplified with high sensitivity and that the refresh operation may be achieved together with the amplifying operation. To this end, a sense amplifier is employed, which is usually of the valanced flip-flop structure. For example, in the case of forming the 16K memory by a (128.times.128) matrix using 128 word lines and 128 bit lines, 128 memory cells are arranged on each bit line and the sense amplifier is positioned at the center of the memory cell array; namely, 64 memory cells are disposed on either side of the sense amplifier, along with a cell which is called a dummy cell. The word line voltage is applied on the word line of the cell on one side of the sense amplifier to be read out and, at the same time it is applied on the word line of the dummy cell on the opposite side where a voltage about one-half of the power source voltage has been stored in the dummy cell. As a result of this, a memory signal is provided on the bit line and various pulses of the sense amplifier start to operate to apply this information to the gate of a flip-flop transistor and the sense amplifier performs a pulse operation so that a minute potential difference between the bit lines on both sides of the sense amplifier may be amplified by the operation of the flip-flop transistor. In the state in which the amplifying operation has once been completed, the potential of the bit line on the side of the cell in which a high-level signal has been stored is already substantially equal to the power source voltage and since the word line is in the conduction voltage level, re-write of the read out memory cell is carried out. The potential of the bit line on the side of the cells in each of which a low-level signal has been stored becomes substantially OV (V.sub.S : ground potential) and OV is also stored in that cell. Amplified signal voltages on these bit lines are applied to an output buffer and an output circuitry to derive therefrom a data out signal. The sense amplifier equipped with such amplifying and refresh functions is disposed on each of 128 bit lines in the case of the abovesaid 16K memory.
Apart from the semiconductor dynamic memory of the one-transistor one-capacitor type in which the operating performance is dependent on the performance of such a high-sensitivity sense amplifier as described above, there is a three-transistor cell type memory represented by Model i-1103 of Intel Inc. which was used as a semiconductor memory and a main memory of a computer for the first time. FIG. 1 shows an equivalent circuit of its memory cell. The readout of this memory is non-destructive unlike in the case of the aforesaid one-transistor one-capacitor type memory. In FIG. 1, reference character Q.sub.1 indicates a write MOS transistor; Q.sub.2 designates a MOS transistor in the gate of which information is stored; and Q.sub.3 identifies a readout transistor. During the write operation, a write select line 2 of the gate of the transisitor Q.sub.1 is in the high voltage level and information from a data input line 1 is stored in a storage capacitance 5 (C.sub.S) of the gate of the transistor Q.sub.2. During the readout operation, a readout select line 4 of the gate of the readout transistor Q.sub.3 is in the high voltage level and when the transistor Q.sub.2 is in the ON state (in the state in which information is stored in the storage capacitance C.sub.S), a current flows via the transistors Q.sub.3 and Q.sub.2, lowering the potential of a readout data line 3. When the transistor Q.sub.2 is in the OFF state (in the state in which data "0" is stored in the storage capacitance C.sub.S), the potential of the readout data line 3 remains high-level. The information stored in the gate of the transistor Q.sub.2 decreases in the form of a leakage current flowing through the transistor Q.sub.1 or in the generation-reconbination process; this information abruptly decreases in about tens of seconds. Before this decrease of the information, however, the same voltage variation is provided on the readout data line 3, no matter how many times the readout select line 4 is in the high voltage level. This is a large difference from the destructive readout operation of the aforementioned one-transistor one-capacitor type dynamic memory in which the memory content disappears when the memory information has once been read out. A large difference between the destructive readout memory and the non-destructive readout memory resides in that, in the former, information stored in a capacitor is directly read out by a current flowing through the capacitor, whereas, in the latter, a voltage stored in the capacitor is read out as voltage information. The three-transistor cell memory shown FIG. 1 calls for three transistors for storing information in one cell. This memory has the advantage that the memory content remains even after reading out the information, but it is inferior to the one-transistor cell type memory in terms of packing density and power consumption. The one-transistor cell type is superior to the three-transistor cell type in terms of large capacity. Accordingly, existing large-scale computers show a marked trend to employ the one-transistor cell type memory as a dynamic memory.